1. Field
Example embodiments relate to a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a method of forming nano dots, method of fabricating a memory device including the same, charge trap layer including the nano dots and memory device including the same.
2. Description of Related Art
As semiconductor technology develops, a method of fabricating memory devices also developed. Volatile or non-volatile memory devices may both be used to store data. However, volatile memory devices, e.g., dynamic random access memories (DRAMs), may lose the stored data when a supply of electric power is stopped. Thus, the volatile memory devices may be used where a relatively large amount of data is stored rather than storing the data for a relatively long time and a more rapid operating speed may be required.
Non-volatile memory devices may store the data for a relatively long time even when the supply of the electric power may be stopped. During the storage of the data for a relatively long time, the data may not be damaged or deformed. The data may be maintained as initially stored in the non-volatile memory devices. Therefore, the non-volatile memory devices may ensure a retention property that may maintain the stored data as initially stored. In addition to the retention property, if a rapid operating speed may be ensured, integrity of the non-volatile memory devices may be increased, and an operating voltage may be reduced.
Such non-volatile memory devices also have the advantages of the volatile memory devices, and thus, may be understood to be a combination of the conventional volatile memory devices and non-volatile memory devices. However, such non-volatile memory devices have not been commercialized, and research and investment has been done to develop these non-volatile memory devices.
Accordingly, non-volatile memory devices having some of the advantages of the volatile memory devices, for example, silicon-oxide-nitride-oxide-silicon (SONOS) memory devices, are being commercialized. Such SONOS memory devices may include a trap layer for trapping electric charges in a gate-stacked structure of a transistor. The gate-stacked structure of the transistor may further include a tunneling layer, a gate electrode, and a blocking layer. The data may be recorded by trapping the electric charges in the trap layer. When a degree of trapping the electric charges may be controlled, multi-bit data may be recorded, and thus, the SONOS memory devices may have a similar integrity as that of DRAM. In the SONOS memory devices, a nitride layer may be used as the trap layer, however, nano dots may also be used as the trap layer.